A CPU consists mainly of registers (places to store values) that have to be controlled by, you guessed it, a control matrix. The control matrix outputs a control word, CON, whose bits activate the needed registers on a computer for input and output. For my computer I am using 3 NVRAM chips to store all of the control words.
The control matrix on my computer has two stages, both of wich consist of 3 steps. The entire sequence is called the machine cycle. And, in my computer’s case, the machine cycle also is equivalent to the instruction cycle which is how long it takes for an instruction to be carried out. The control logic is driven by a ring counter which activates 6 outputs one at a time with each clock pulse. On the first high bit of the ring counter an 8-bit counter that addresses the control ROM is cleared. On the third high bit of the ring counter an address is loaded into the counter from an 8-bit ROM that is addressed by a 4-bit OP code that tells the counter where the instruction steps are held inside of the ROM. I built a rudimentary programmer that takes breadboard wires moved to either positive voltage or ground as input.
My Programmer
If you enjoyed this article, please consider sharing it!
My brother recommended I might like this web site. He was once entirely right. This put up truly made my day. You cann’t believe simply how much time I had spent for this info! Thanks!
When the control matrix outputs the RO,AI control word how do you keep the timing right? What if the program memory stops outputting before the A register can input the value. I tested it in a circuit simulator and it did not work correctly with the timing issues.
I’m not exactly sure what is causing that problem for you. If I recall correctly, when the control matrix sent out the (~RO,~AI) control, and then the A register was updated with the addressed byte in memory on the next rising clock pulse. Perhaps you are trying to run the control matrix and the registers on the same clock cycle. I set the structure of my computer up so that the control words for each OP are output on the falling clock pulses, and the registers are updated on the rising. The time in-between rising and falling pulses should be well enough for the memory to set up the current byte for loading.
How are the registers only updated on the rising clock pulse? The diagrams only had the input and output pins on the registers. Is there a pin not shown?